sn54act564, sn74act564 octal d-type edge-triggered flip-flops with 3-state outputs scas549a november 1995 revised may 1996 1 post office box 655303 ? dallas, texas 75265 inputs are ttl-voltage compatible epic ? (enhanced-performance implanted cmos) 1- m m process 3-state inverted outputs drive bus lines directly flow-through architecture to optimize pcb layout full parallel access for loading package options include plastic small-outline (dw), shrink small-outline (db), thin shrink small-outline (pw), ceramic chip carriers (fk) and flatpacks (w), and standard plastic (n) and ceramic (j) dips description the 'act564 are octal d-type edge-triggered flip-flops that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. they are particu- larly suitable for implementing buffer registers, i/o ports, bidirectional bus drivers, and working registers. on the positive transition of the clock (clk) input, the q outputs are set to the complements of the logic levels set up at the data (d) inputs. a buffered output-enable (oe ) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. in the high-impedance state, the outputs neither load nor drive the bus lines significantly. the high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. oe does not affect internal operations of the flip-flops. old data can be retained or new data can be entered while the outputs are in the high-impedance state. the sn54act564 is characterized for operation over the full military temperature range of 55 c to 125 c. the sn74act564 is characterized for operation from 40 c to 85 c. function table (each flip-flop) inputs output oe clk d q l h l l lh l h or l x q 0 h x x z 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 oe 1d 2d 3d 4d 5d 6d 7d 8d gnd v cc 1q 2q 3q 4q 5q 6q 7q 8q clk sn54act564 ...j or w p ackage sn74act564 . . . db, dw, n, or pw package (top view) 3 2 1 20 19 910111213 4 5 6 7 8 18 17 16 15 14 2q 3q 4q 5q 6q 3d 4d 5d 6d 7d 2d 1d oe 8q 7q 1q 8d gnd clk v cc sn54act564 . . . fk package (top view) unless otherwise noted this document contains production data information current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. copyright ? 1996, texas instruments incorporated please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. epic is a trademark of texas instruments incorporated.
sn54act564, sn74act564 octal d-type edge-triggered flip-flops with 3-state outputs scas549a november 1995 revised may 1996 2 post office box 655303 ? dallas, texas 75265 logic symbol 2 logic diagram (positive logic) oe 1d 2 1d 3 2d 4 3d 5 4d 6 5d 19 18 17 16 15 14 13 12 7 6d 8 7d 9 8d en 1 oe clk 1d 1q 1 11 2 19 to seven other channels c1 1d 1q 2q 3q 4q 5q 6q 7q 8q 1 11 clk c1 2 this symbol is in accordance with ansi/ieee std 91-1984 and iec publication 617-12. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 3 supply voltage range, v cc 0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i (see note 1) 0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range, v o (see note 1) 0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0 or v i > v cc ) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0 or v o > v cc ) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous output current, i o (v o = 0 to v cc ) 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous current through v cc or gnd 200 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . maximum power dissipation at t a = 55 c (in still air) (see note 2): db package 0.6 w . . . . . . . . . . . . . . . . . dw package 1.6 w . . . . . . . . . . . . . . . . . n package 1.3 w . . . . . . . . . . . . . . . . . . . pw package 0.7 w . . . . . . . . . . . . . . . . . storage temperature range, t stg 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. the input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. the maximum package power dissipation is calculated using a junction temperature of 150 c and a board trace length of 750 mils, except for the n package, which has a trace length of zero.
sn54act564, sn74act564 octal d-type edge-triggered flip-flops with 3-state outputs scas549a november 1995 revised may 1996 3 post office box 655303 ? dallas, texas 75265 recommended operating conditions (see note 3) sn54act564 sn74act564 unit min max min max unit v cc supply voltage 4.5 5.5 4.5 5.5 v v ih high-level input voltage 2 2 v v il low-level input voltage 0.8 0.8 v v i input voltage 0 v cc 0 v cc v v o output voltage 0 v cc 0 v cc v i oh high-level output current 24 24 ma i ol low-level output current 24 24 ma d t/ d v input transition rise or fall rate 0 8 0 8 ns/v t a operating free-air temperature 55 125 40 85 c note 3: unused inputs must be held high or low to prevent them from floating. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions v cc t a = 25 c sn54act564 sn74act564 unit parameter test conditions v cc min typ max min max min max unit i oh =50 m a 4.5 v 4.4 4.49 4.4 4.4 i oh = 50 m a 5.5 v 5.4 5.49 5.4 5.4 v oh i oh =24ma 4.5 v 3.86 3.7 3.76 v v oh i oh = 24 ma 5.5 v 4.86 4.7 4.76 v i oh = 50 ma 2 5.5 v 3.85 i oh = 75 ma 2 5.5 v 3.85 i ol =50 m a 4.5 v 0.1 0.1 0.1 i ol = 50 m a 5.5 v 0.1 0.1 0.1 v ol i ol =24ma 4.5 v 0.36 0.5 0.44 v v ol i ol = 24 ma 5.5 v 0.36 0.5 0.44 v i ol = 50 ma 2 5.5 v 1.65 i ol = 75 ma 2 5.5 v 1.65 i oz v o = v cc or gnd 5.5 v 0.25 5 2.5 m a i i v i = v cc or gnd 5.5 v 0.1 1 1 m a i cc v i = v cc or gnd, i o = 0 5.5 v 4 80 40 m a d i cc 3 one input at 3.4 v, other inputs at gnd or v cc 5.5 v 0.6 1.6 1.5 ma c i v i = v cc or gnd 5 v 4.5 pf c o v o = v cc or gnd 5 v 15 pf 2 not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms. 3 this is the increase in supply current for each input that is at one of the specified ttl voltage levels rather than 0 v or v cc . timing requirements over recommended operating free-air temperature range, v cc = 5 v 0.5 v (unless otherwise noted) (see figure 1) t a = 25 c sn54act564 sn74act564 unit min max min max min max unit t w pulse duration, clk high or low 3 5 3.5 ns t su setup time, data before clk 2.5 3.5 3 ns t h hold time, data after clk 1 2.5 1 ns product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice.
sn54act564, sn74act564 octal d-type edge-triggered flip-flops with 3-state outputs scas549a november 1995 revised may 1996 4 post office box 655303 ? dallas, texas 75265 switching characteristics over recommended operating free-air temperature range, v cc = 5 v 0.5 v (unless otherwise noted) (see figure 1) parameter from to t a = 25 c sn54act564 sn74act564 unit parameter (input) (output) min typ max min max min max unit f max 85 90 65 75 mhz t plh clk q 2 6.5 10.5 1 12.5 1.5 11.5 ns t phl clk q 1.5 6 9.5 1 11.5 1.5 10.5 ns t pzh oe q 1.5 5.5 9 1 10.5 1.5 9.5 ns t pzl oe q 1.5 5.5 8.5 1 10.5 1 9.5 ns t phz oe q 1.5 7 10.5 1 12.5 1.5 11.5 ns t plz oe q 1.5 5 8 1 9.5 1 8.5 ns operating characteristics, v cc = 5 v, t a = 25 c parameter test conditions typ unit c pd power dissipation capacitance c l = 50 pf, f = 1 mhz 50 pf product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice.
sn54act564, sn74act564 octal d-type edge-triggered flip-flops with 3-state outputs scas549a november 1995 revised may 1996 5 post office box 655303 ? dallas, texas 75265 parameter measurement information 0 v 0 v t h t su voltage waveforms data input t plh t phl v oh v ol 0 v input output timing input voltage waveforms from output under test c l = 50 pf (see note a) load circuit s1 2 v cc 500 w 500 w output control (low-level enabling) output waveform 1 s1 at 2 v cc (see note b) output waveform 2 s1 at open (see note b) v ol v oh t pzl t pzh t plz t phz v cc 0 v v ol + 0.3 v 0 v open voltage waveforms t plh /t phl t plz /t pzl t phz /t pzh open 2 v cc open test s1 3 v 0 v t w voltage waveforms input v oh 0.3 v 1.5 v 1.5 v 1.5 v 3 v 3 v 1.5 v 1.5 v 1.5 v 1.5 v 3 v 50% v cc 50% v cc 1.5 v 1.5 v 3 v 50% v cc 50% v cc notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 1 mhz, z o = 50 w , t r 2.5 ns, t f 2.5 ns. d. the outputs are measured one at a time with one input transition per measurement. figure 1. load circuit and voltage waveforms
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1998, texas instruments incorporated
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